analog w devices 01 cmos protected dual spst analog switch adg200 features latch.proof di cmos overvoltage.proof: vsuppl y :!:25v superior dg-200 replacement break-before-make switching action ron: 100n max over full temperature range direct ttl/cmos interface general description the adg200 is a dual single-pole-single-throw analog switch. in the on condition, the switch conducts current in either direction, maintaining nearly constant on resistance over the entire analog signal range. in the off condition, the switch blocks voltages of peak values equal to the switch v + and v- supplies. switch action is break-before-make. the digital in- puts interface directly to ttl or cmos logic over the full operating temperature range. fabricated using an advanced monolithic dielectric ally-isolated cmos process, the adg200 is a superior plug-in replacement for the dg200. the adg200 provides additional advantages (over the dg200) of: overvoltage protection to :!:25v beyond the power supplies, total latch-free operation, much lower power dissipation (30mw max) and faster switching time. ordering information commercial 0 to +70c plastic industrial -2soc to +8soc military -ssoc to +l2soc ceramic to-loo ceramic to-too adg200aa adg200aa/883 adg200cj adg200bp ADG200BA adg200ap note: "/883" version is 100% screened to mil-sto-883, class b as per note 7, page 2. information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implica- tion or otherwise under any patent or patent rights of analog devices. ---- pin configuration to-100 dual-in-line package vi d2 top view top view switch states are for logic "1" input (positive logic) route 1 industrial park; p.o. box 280; norwood, mass. 02062 tel: 617/329-4700 twx: 710/394-6577 west coast mid-west texas 714/842-1717 312/894-3300 214/231-5094 ~- ~ obsolete
specifications notes, . typical values for information only, not guaADG200BA 3.50 3.00 2.50 2.25 2.00 adg200aa 11.00 9.00 7.75 7.75 7.00 adg200aa/88 3 7 15.00 12_75 11.25 11.25 10.75 obsolete
circuit description ~al~~~j ~"-'~t\ v1 note, logic "0" on in terminal closes switch between s ano o. figure 1. schematic diagram (1 of 2 channels) cmos devices make excellent analog switches; however, prob- lems with overvoltage and latch-up phenomenon necessitate protection circuitry. however, these protection circuits either cause degradation of important switch parameters such as ron or leakage, or provide only limited protection in the event of overvoltage. the adg200 switch utilizes a dielectric ally-isolated cmos fabrication process to eliminate the four-layer structure found in junction-isolated cmos, thus providing latch-free operation. a typical switch channel is shown in figure 1. the output switching element consists of device numbers 17 and 20. operation is as follows: for an "on" switch, the gate of device 20 is vi and the gate of device 17 is v2 from the driver circuits. device numbers 14, 15, and 16 are "off" and numbers 18 and 19 are "on". hence, the back-gates of the p- and n-channel output devices (numbers 17 and 20) are tied together and floating. floating the output switch back-gates with the signal input provides a flatter ron versus vs response. for an "off" switch, device numbers 18 and 19 are "off", and the back-gates of devices 17 and 20 are tied through lkn resistors r3 and r4 to the respective supply voltages through the "on" devices 14,15, and 16. d figure 2. adg200 output switch diode equivalent circuit if a voltage is applied to the s or d terminals which exceeds vi or v2, the s- or d-to-back-gate diode is forward biased; however, r3 and r4 provide current limiting action (fig. 2). consequently, without external current limiting resistance (or increased ron)' the adg200 series switches provide: 1. latch-proof operation. 2. overvoltage protection 25v beyond the vi or v2 supply voltage. an equivalent circuit of the output switch element in figure 2 shows that, indeed, the lkn limiting resistors are in series with the back-gates of the p- and n-channel output devices- not in series with the signal path between the s & d terminals. in some applications it is possible to run on a parasitic npn (drain to back-gate to source of the n-channel) transistor which causes device destruction under certain conditions. this case will only manifest itself when a negative overvoltage (and not a positive overvoltage) exists with another voltage source on the other side of the switch. current limitation through external resistors (200n) or the output of op amps will prevent damage to the device. _'l v1 +15v p+ n- f" p+ so . t- p channel n-channel n+ p- n+ 1k b -15v v2 obsolete
typical performance characteristics 500 v, =+15v v2 =-15v vin =ov to 5v 400 i!! i w :ie 300 j: ci z i 2 0 0 ~ i 0 25 45 65 85 105 temperature - c 125 figure 3. switching time vs. temperature 2.0 0 ~ ~ i x > 1.5 1.0 ta =+25c 0.5 0 7 8 9 10 11 12 v,= iv21 - volts 13 14 15 figure 4. input logic threshold vs. power supply voltage bonding diagram dimensions shown in inches and (mm). inz in, gnd 01 v1 i 00 '" s2 s1 |
